Third generation wireless communication standards, such as UMTS/FDD, TDD, IS2000, and TD-SCDMA, operate at very high frequencies. Modems (tansceivers) for 3G mobile communication standards such as UMTS require approximately 100 times more digital signal processing power than GSM. It is desired to implement a transceiver for such standards using a programmable architecture in order to be able to deal with different standards and to be able to flexibly adapt to new standards. Using conventional DSP technology operating at conventional frequencies could require as many as 30 DSPs to provide the necessary performance. It will be clear that such an approach is neither cost-effective nor power efficient compared to conventional hardware-based approaches of transceivers for single-standards.
A known approach to increasing performance of a processor is to use a vector architecture. In a vector processor, a vector consists of more than one data element, for example sixteen 16-bit elements. A functional unit of the processor operates on all individual data elements of the vector in parallel, triggered by one instruction. Using a pipelined vector processor, the performance can be increased further.
Vector processors have traditionally mainly been used for scientific processing. In principle, vector processors can also be used for signal processing. However, the conventional vector processor architecture is ineffective for applications that are not 100% vectorizable, due to the implications of what is known as “Amdahl's Law”. This law states that the overall speedup obtained from vectorization on a vector processor with P processing elements, as a function of the fraction of code that can be vectorized (f), equals (1−f+f/P)−1. This means that when 50% of the code can be vectorized, an overall speedup of less than 2 is realized (instead of the theoretical maximum speedup of 32). This is because the remaining 50% of the code cannot be vectorized, and thus no speedup is achieved for this part of the code. Even if 90% of the code can be vectorized, the speedup is still less than a factor of 8. For use in consumer electronics applications, in particular mobile communication, the additional costs of a vector processor can only be justified if a significant speed-up can be achieved.